Electronic packages and similar products which include organic laminate substrates have been and continue to be developed for many of today's applications. One primary example of such a product is a chip carrier sold under the name HyperBGA by the Assignee of this invention, Endicott Interconnect Technologies, Inc. (HyperBGA is a registered trademark of Endicott Interconnect Technologies, Inc.) These carriers are able to accommodate one or more semiconductor chips thereon and therefore are able to displace the earlier developed ceramic substrates in many chip carrier applications, primarily because of reduced cost and enhanced electrical performance. The use of a multi-layered interconnect structure such as an organic, laminate chip carrier for interconnecting a semiconductor chip to a printed circuit board in an electronic package introduces many challenges. One of the most significant challenges facing such highly miniaturized products is the challenge to provide the necessary, highly dense circuit patterns able to conduct the high frequency (speed) signals from the positioned chip(s) to the underlying supporting substrate on which the carrier is positioned.
As semiconductor chip input/output (I/O) counts increase (especially beyond the capability of peripheral lead devices) and as the need for both semiconductor chip and printed circuit board miniaturization increases, carriers of the type defined above offer the best practical solutions to interconnecting the chips and underlying PCB. In order to satisfactorily provide such interconnection, however, the carrier circuitry itself must assure optimum signal passage. That is, there can be virtually no impediments to effective, high frequency signal transference through the package itself. As understood from the following, one of the main aspects of the present invention is to provide a method of making a substrate with enhanced wiring (circuitry) in which different levels of circuitry within the substrate are effectively interconnected in such a manner that high densification is reliably assured. These interconnections are provided by plated through holes (hereinafter also PTH's) which are formed in a new and unique manner to function cooperatively with other circuit wiring (e.g., lines) connected thereto to provide enhanced paths for the signals passing there-through. It is believed that such a method will constitute a significant advancement in the art.
Various electronic packages and methods relating to the manufacture of the substrates thereof are defined in the following U.S. Letters Patents. This list is not all-inclusive however, as it is fully understood that there are many additional patents which also describe various packages and methods. The following is thus meant only to be representative of some of those known in the art. The listing is not an admission that any of those identified are prior art to the present invention.
In U.S. Pat. No. 7,035,113, there is defined a multi-chip electronic package which utilizes an organic, laminate chip carrier and a plurality of semiconductor chips positioned on an upper surface of the carrier. The organic, laminate chip carrier is comprised of a plurality of conductive planes and dielectric layers and couples the chips to underlying conductors on the bottom surface thereof. The carrier may include a high-speed portion to assure high-frequency connection between the semiconductor chips and may also include an internal capacitor and/or thermally conductive member for enhanced operational capabilities. U.S. Pat. No. 7,035,113 is assigned to the same assignee as the present invention.
In U.S. Pat. No. 7,024,764, there is described a method of making an electronic package. The method includes forming a semiconductor chip and a multi-layered interconnect structure. The semiconductor chip includes a plurality of contact members on one of its surfaces that are connected to the multi-layered interconnect structure by a plurality of solder connections. The formed multi-layered interconnect structure is adapted for electrically interconnecting the semiconductor chip to a circuit board with another plurality of solder connections and includes a thermally conductive layer comprised of a material having a selected thickness and coefficient of thermal expansion to substantially prevent failure of the solder connections between said first plurality of electrically conductive members and the semiconductor chip. The method forms the electronic package to further include a dielectric material having an effective modulus to assure sufficient compliancy of the multi-layered interconnect structure during operation.
In U.S. Pat. No. 6,992,896, there is defined a multi-chip electronic package which utilizes an organic, laminate chip carrier and a pair of semiconductor chips positioned on an upper surface of the carrier in a stacked orientation. The organic, laminate chip carrier is comprised of a plurality of conductive planes and dielectric layers and couples one or both of the chips to underlying conductors on the bottom surface thereof. The carrier may include a high-speed portion to assure high-frequency connection between the semiconductor chips and may also include an internal capacitor and/or thermally conductive member for enhanced operational capabilities. The first chip, e.g., an ASIC chip, is solder bonded to the carrier while the second chip, e.g., a memory chip, is secured to the first chip's upper surface and coupled to the carrier using a plurality of wire-bond connections. U.S. Pat. No. 6,992,896 is also assigned to the same assignee as the present invention.
In U.S. Pat. No. 6,815,837, there is defined an electronic package and information handling system utilizing same wherein the package's substrate includes an internally conductive layer coupled to an external pad and of a size sufficiently large enough to substantially prevent cracking, separation, etc. of the pad when the pad is subjected to a tensile pressure of about 1.4 grams per square mil or greater. U.S. Pat. No. 6,815,837 is also assigned to the same assignee as the present invention.
In U.S. Pat. No. 6,483,074, there is described a laser system for micro via formation directly over a plated through hole (PTH) within a printed circuit board. The laser system forms the micro via directly over the PTH with full dielectric removal from a capture pad while maintaining the dielectric within the PTH to a substantially flush level with the surface of the capture pad. This patent states that it is undesirable to remove dielectric from the hole and hence the reason for leaving the dielectric at the flush level. This patent further states that conventional Gaussian distribution and uniform distribution are less desirable because these energy distributions tend to remove dielectric material within the opening of the PTH, which may lead to reliability problems caused by entrapped plating solution. It will be understood from the teachings herein that the present invention represents a significant improvement over the process defined in U.S. Pat. No. 6,483,074 because it teaches removal of dielectric from within a PTH to a selected level sufficient that the interior walls of the PTH may be plated with metal as well as the exposed upper surface of the dielectric within the lower PTH. The advantages of such a “capped” arrangement are explained in the instant application.
In U.S. Pat. No. 6,351,393, there is described an electronic package and method of making the electronic package wherein the package includes a semiconductor chip and a multi-layered interconnect structure. The semiconductor chip includes a plurality of contact members on one of its surfaces that are connected to the multi-layered interconnect structure by a plurality of solder connections. The multi-layered interconnect structure is adapted for electrically interconnecting the semiconductor chip to a circuitized substrate (eg., circuit board) with another plurality of solder connections and includes a thermally conductive layer being comprised of a material having a selected thickness and coefficient of thermal expansion to substantially prevent failure of the solder connections between said first plurality of electrically conductive members and the semiconductor chip. The electronic package further includes a dielectric material having an effective modulus to assure sufficient compliancy of the multi-layered interconnect structure during operation.
In U.S. Pat. No. 6,040,552, there is described a via-drilling system for forming vias in substrates, and more particularly to a low-cost, high-throughput drilling system for micro-via arrays, wherein energy from a single high-energy laser beam is multiplexed into multiple sub-beams to provide a related finite number of patterning beam lines, each beam line being equipped with appropriate mask-projection optics, for simultaneously drilling a finite number of separate, high-quality, mask-controlled multiple-micro-via patterns into a substrate.
In U.S. Pat. No. 5,798,563, there is described an organic chip carrier for use with flip chips, comprising an organic dielectric layer, a first layer of circuitry disposed on the dielectric layer, an organic conformational coating disposed over the first layer of dielectric and the first layer of circuitry, and a layer of fine line circuitry having line width of about 2.0 mil or less, preferably about 1.0 mil or less, preferably about 0.7 mil, and a space between lines of about 1.5 mil or less, preferably about 1.1 mil or less, disposed on the conformational layer. Preferably the dielectric layer is free of woven fiber glass. The conformational coating preferably has a dielectric constant of about 1.5 to about 3.5, and a percent planarization of greater than about 3.5%.
In U.S. Pat. No. 5,574,630, there is described a power/ground structure and associated PCB in which the coefficient of thermal expansion (CTE) of the power/ground structure and associated circuit board are closely matched to each other. The PCB is formed of organic electrically-insulating material having electrical circuitry thereon which carries an integrated circuit chip. The power/ground assembly is formed of alternating layers of organic insulating material and at least two layers of electrically-conducting material, typically copper, one of the layers of electrically-conducting material forming a power connection and another layer of the electrically-conducting material forming a ground plane. There is also at least one additional layer of a structural material having a relatively high Young's Modulus and a CTE of less than about 10 PPM/.degree C. Invar or copper clad Invar are preferred materials for this structure. The electrically-conducting copper material and the Invar are selected in thickness and number such that, together with the electrically-insulating material, the composite CTE of the power/ground structure closely matches that of the circuit card or board.
In U.S. Pat. No. 5,539,175, there is described both method and apparatus for laser ablation of openings with a specified wall profile in materials such as polyimide. The method includes identifying the opening profile of choice. This profile of choice is then divided into convex portions which can be “stably” formed and concave portions which are “unstably” formed. With respect to convex portions of apertures, after ablation to their desired depth, these convex portions remain substantially unchanged with additional exposure to otherwise ablating radiation. With respect to concave portions of apertures, these concave portions change with additional exposure to ablating radiation. Accordingly, techniques are disclosed for controlling exposure to ablating radiation, controlling the profile of the ablating radiation, or both. In either case, the intensity profile of the working image containing the ablating light is shaped in accordance with the depth and slope of the sidewalls of the opening desired. Intensity of the working image is tailored across the opening to levels above the ablation threshold in accordance with the desired wall shape. Exposure to ablating radiation occurs with this exposure closely monitored only in the case of unstable concave profiles. The technique can be practiced with imaging systems or, preferably, practiced with masks containing computer generated holograms where light efficiencies are improved.
As mentioned above, the present invention represents a significant improvement in the art of manufacturing circuitized substrates, including particularly over the process defined in U.S. Pat. No. 6,483,074 cited above, because it teaches the formation of a “capped” or interlocking arrangement of vertically oriented conductive through-holes, thereby assuring a sound, effective connection between adjacent conductive elements in a multi-layered substrate structure. The invention is able to do so in a highly dense pattern, if needed, to thus meet today's more stringent operational requirements for products using such substrates. Other advantages of the invention are discernible from the teachings herein. It is believed that such an invention will represent a significant advancement in the art.